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19-3209; Rev 1; 2/09
KIT ATION EVALU ABLE AVAIL
Low-Power Audio/Video Switch for Dual SCART Connectors
General Description
The MAX9598 dual SCART matrix routes audio and video signals between a set-top box decoder chip and two external SCART connectors under I2C control. Operating from a 3.3V supply and a 12V supply, the MAX9598 consumes 70mW during quiescent operation and 471mW during average operation when driving typical signals into typical loads. Video input detection, video load detection, and a 1.7mW low-power mode facilitate the design of lowpower set-top boxes. The MAX9598 audio section contains a buffered crosspoint to route audio inputs to audio outputs. The DirectDrive(R) output amplifiers create a 2VRMS full-scale audio signal biased around ground, eliminating the need for bulky output capacitors and reducing clickand-pop noise. The zero-cross detection circuitry also further reduces clicks and pops by enabling audio sources to switch only during a zero-crossing. The MAX9598 video section contains a buffered crosspoint to route video inputs to video outputs. The standarddefinition video signals from the set-top box decoder chip are lowpass filtered to remove out-of-bandwidth artifacts. The MAX9598 also supports slow-switching and fast-switching signals. An interrupt signal from the MAX9598 informs the microcontroller (C) when the system status has changed. The MAX9598 is available in a compact 40-pin thin QFN package and is specified over the 0C to +70C commercial temperature range.
DirectDrive is a registered trademark of Maxim Integrated Products, Inc.
Features
70mW Quiescent Power Consumption 1.7mW Low-Power Mode Consumption 0.1mW Shutdown Consumption Clickless/Popless, DirectDrive Audio Video Input Detection Video Load Detection Video Reconstruction Filter with 10MHz Passband and 52dB Attenuation at 27MHz 3.3V and 12V Supply Voltages
MAX9598
Applications
Set-Top Boxes TVs DVD Players
Ordering Information
PART MAX9598CTL+ TEMP RANGE 0C to +70C PIN-PACKAGE 40 TQFN-EP*
+Denotes a lead(Pb)-free/RoHS-compliant package. *EP = Exposed pad.
System Block Diagram
V12 12V STB CHIP I2C C INTERRUPT OUTPUT VVID 3.3V VAUD 3.3V
MAX9598
RGB, Y/C, CVBS I2C INTERFACE AND REGISTERS CVBS L/R AUDIO TV SCART
VIDEO ENCODER STEREO AUDIO DAC
RGB, Y/C, CVBS
VIDEO FILTERS AND CROSSPOINT AUDIO CROSSPOINT WITH DirectDrive OUTPUTS SLOW SWITCHING FAST SWITCHING CHARGE PUMP EP GNDVID
SLOW SWITCHING FAST SWITCHING
SINGLE-ENDED STEREO AUDIO
Y/C, CVBS RGB, Y/C, CVBS L/R AUDIO SLOW SWITCHING FAST SWITCHING VCR SCART
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
ABSOLUTE MAXIMUM RATINGS
VVID to GNDVID ...................................................-0.3V to +4V V12 to EP .............................................................-0.3V to +14V VAUD to EP ............................................................-0.3V to +4V EP to GNDVID .....................................................-0.1V to +0.1V All Video Inputs, VCRIN_FS to GNDVID ................-0.3V to +4V All Audio Inputs to EP.......................................-1V to (EP + 1V) SDA, SCL, DEV_ADDR, INT to GNDVID ............ ...-0.3V to +4V TV_SS, VCR_SS to EP ..............................-0.3V to (V12 + 0.3V) Current All Video/Audio Inputs................................................20mA C1P, C1N, CPVSS ......................................................50mA Output Short-Circuit Current Duration All Video Outputs, TVOUT_FS to VVID, GNDVID ...Continuous Audio Outputs to VAUD, EP ...................................Continuous TV_SS, VCR_SS to V12, EP ....................................Continuous Continuous Power Dissipation (TA = +70C) 40-Pin Thin QFN (derate 26.3mW/C above +70C) ..........................2105.3mW Operating Temperature Range ..............................0C to +70C Junction Temperature .....................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Video Supply Voltage Range Audio Supply Voltage Range V12 Supply Voltage Range SYMBOL VVID VAUD V12 CONDITIONS Inferred from video PSRR test at 3V and 3.6V Inferred from audio PSRR test at 3V and 3.6V Inferred from slow-switching levels Normal operation (Note 2), with all video outputs enabled and muted VVID Quiescent Supply Current IVID_Q Low-power mode Shutdown VAUD Quiescent Supply Current IAUD_Q Normal operation (Note 2) Shutdown POR state V12 Quiescent Supply Current I12_Q Normal operation (Note 2) Shutdown VIDEO CHARACTERISTICS DC-COUPLED INPUT Input Voltage Range Input Current Input Resistance AC-COUPLED INPUT Sync-Tip Clamp Level Sync Crush VCLP Sync-tip clamp Sync-tip clamp, percentage reduction in sync pulse (0.3VP-P), guaranteed by input clamping current measurement -13 -3.5 +6 2 mV % VIN IIN RIN RL = 75 to GNDVID or 150 to VVID/2, inferred from gain test VIN = 0.3V VVID = 3V VVID = 3.135V VVID = 3.3V 1.3 1 300 5 A k 1.15 1.2 VP-P Slow-switching output sets to medium level MIN 3 3 11.4 TYP 3.3 3.3 12 18.2 500 18.4 2.7 12 3 475 0.25 10 MAX 3.6 3.6 12.6 30 1000 32 6 25 100 A UNITS V V V mA A mA A
2
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Low-Power Audio/Video Switch for Dual SCART Connectors
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Input Clamping Current Maximum Input Source Resistance Bias Voltage Input Resistance DC CHARACTERISTICS DC Voltage Gain Av VBIAS Bias circuit Bias circuit Guaranteed by output-voltage swing Guaranteed by output-voltage swing of TV_R/C_OUT, TV_G_OUT, and TV_B_OUT; first input signal set is VCR_R/C_IN, VCR_G_IN, and VCR_B_IN; second signal set is ENC_R/C_IN, ENC_G_IN, and ENC_B_IN Sync-tip clamp (VIN = VCLP) Bias circuit Sync-tip clamp, measured at output, VVID = 3V, VIN = VCLP to (VCLP +1.15V), RL = 150 to VVID/2, RL = 75 to GNDVID Measured at output, VVID = 3.135V, VIN = VCLP to (VCLP +1.2V), RL = 150 to VVID/2, RL = 75 to GNDVID Bias circuit, measured at output, VVID = 3V, VIN = (VBIAS - 0.575V) to (VBIAS + 0.575V), RL = 150 to VVID/2, RL = 75 to GNDVID Measured at output, VVID = 3.135V, VIN = (VBIAS - 0.6V) to (VBIAS + 0.6V), RL = 150 to VVID/2, RL = 75 to GNDVID Output Short-Circuit Current Output Resistance Output Leakage Current Power-Supply Rejection Ratio AC CHARACTERISTICS Filter Passband Flatness Filter Attenuation Slew Rate Settling Time Differential Gain Differential Phase 2T Pulse-to-Bar K Rating DG DP VOUT = 2VP-P, f = 100kHz to 10MHz VOUT = 2VP-P, attenuation is referred to 100kHz f = 11MHz f = 27MHz f = 54MHz -1 3 52 55 60 400 0.15 0.6 0.3 V/s ns %
Degrees
MAX9598
SYMBOL
CONDITIONS Sync-tip clamp, VIN = 0.3V
MIN
TYP 1 300
MAX 2
UNITS A
0.57
0.60 10
0.63
V k
1.95
2
2.05
V/V
DC Gain Mismatch Between R, G, and B Outputs
-2
+2
%
Output Level
0.19 1.35
0.30 1.50 2.3
0.40 1.62
V
2.34
2.40
2.46 VP-P
Output-Voltage Swing
2.3
2.34
2.40 100
2.46 mA 10 A dB dB dB
ROUT Output disabled (load detection not active) 3V VVID 3.6V 50
0.5
VOUT = 2VP-P, no filter in video path VOUT = 2VP-P, settle to 0.1% (Note 3) 5-step modulated staircase, f = 4.43MHz 5-step modulated staircase, f = 4.43MHz 2T = 200ns, bar time is 18s; the beginning 2.5% and the ending 2.5% of the bar time are ignored
K%
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER 2T Pulse Response 2T Bar Response Nonlinearity Group Delay Distortion Glitch Impulse Caused by Charge-Pump Switching Peak Signal-to-RMS Noise Power-Supply Rejection Ratio Output Impedance Video Crosstalk Reverse Isolation SYMBOL 2T = 200ns 2T = 200ns, bar time is 18s; the beginning 2.5% and the ending 2.5% of the bar time are ignored 5-step staircase 100kHz f 5MHz, outputs are 2VP-P Measured at outputs 100kHz f 5MHz f = 100kHz, 100mVP-P f = 5MHz f = 4.43MHz VCR SCART inputs to encoder inputs, fullpower mode with VCR being looped through to TV, f = 4.43MHz Enable VCR_R/C_OUT pulldown through I2C interface VIN = -0.707V to +0.707V VIN = -0.707V to +0.707V f = 20Hz to 20kHz, 0.25VRMS input 0.25VRMS input, frequency where output is -3dB referenced to 1kHz No sustained oscillations, 75 series resistor on output VIN = -0.707V to +0.707V VIN = 0V f = 1kHz, THD < 1% No input signal, VIN grounded f = 1kHz, 0.25VRMS input, 20Hz to 20kHz RL = 3.33k, f = 1kHz, 0.25VRMS input RL = 3.33k, f = 1kHz, 0.5VRMS input f = 1kHz DC f = 1kHz f = 1kHz, 0.25VRMS input f = 1kHz, 0.25VRMS input 75 -3 97 0.0014 0.001 0.4 100 90 110 92 0.5 +3 3.95 -1.5 0.006 230 300 10 500 CONDITIONS MIN TYP 0.2 0.2 0.1 11 100 70 42 2 -46 92 MAX UNITS K% K% % ns pVs dB dB dB dB
Pulldown Resistance AUDIO CHARACTERISTICS Voltage Gain Gain Mismatch Flatness Frequency Bandwidth Capacitive Drive Input Resistance Input Bias Current Input Signal Amplitude Output DC Level Signal-to-Noise Ratio Total Harmonic Distortion Plus Noise Output Impedance Power-Supply Rejection Ratio Mute Suppression Audio Crosstalk
4.6
7.5
4
4.05 +1.5
V/V % dB kHz pF M nA VRMS mV dB % dB dB dB
4
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER VIDEO-TO-AUDIO INTERACTION Crosstalk CHARGE PUMP Switching Frequency FAST SWITCHING Input Low Input High Level Input Current Output Low Voltage Output High Voltage Output Resistance Rise Time Fall Time SLOW SWITCHING Input Low Voltage Input Medium Voltage Input High Voltage Input Current Output Low Voltage Output Medium Voltage Output High Voltage DIGITAL INTERFACE Input High Voltage Input Low Voltage Input Hysteresis Input Leakage Current Input Capacitance 0.1VVID < SDA < 3.3V, 0.1VVID < SCL < 3.3V, I/O pins of fast-mode devices must not obstruct the SDA and SCL lines if V+ is switched off VOL fSCL tBUF tHD, STA ISINK = 6mA 0 1.3 0.6 VIH VIL VHYS IIH, IIL -1 6 0.7 x VVID 0.3 x VVID 0.06 x VVID +1 V V V A pF 10k to EP, 11.4V V12 12.6V 10k to EP, 11.4V V12 12.6V 10k to EP, 11.4V V12 12.6V 5 10 4.5 9.5 70 100 1.5 6.5 2 7 V V V A V V V 143 to GNDVID 143 to GNDVID IOL = 0.5mA IOH = 0.5mA VVID - 0.1 7 12 10 1 10 0.1 0.4 V V A V V ns ns 580 kHz Video input: f = 15kHz, 1VP-P signal, Audio input: f = 15kHz, 0.5VRMS signal 92 dB SYMBOL CONDITIONS MIN TYP MAX UNITS
Input Current
-10
+10
A
Output Low Voltage SDA Serial Clock Frequency Bus Free Time Between a STOP and a START Condition Hold Time, (Repeated) START Condition
0.4 400
V kHz s s
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5
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
ELECTRICAL CHARACTERISTICS (continued)
(V12 = 12V, VVID = VAUD = 3.3V, VGNDVID = VEP = 0V, no load, TA = 0C to +70C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Low Period of the SCL Clock High Period of the SCL Clock Setup Time for a Repeated START Condition Data Hold Time Data Setup Time Fall Time of SDA Transmitting Setup Time for STOP Condition Pulse Width of Spike Suppressed OTHER DIGITAL I/O DEV_ADDR Low Level DEV_ADDR High Level DEV_ADDR Input Current Interrupt Output Low Voltage Interrupt Output Leakage Current IOL = 0.5mA INT high impedance 0.7 x VVID -1 +1 0.1 10 0.3 x VVID V V A V A SYMBOL tLOW tHIGH tSU, STA tHD, DAT tHD, DAT tF tSU, STO tSP Input filters on the SDA and SCL inputs suppress noise spikes less than 50ns ISINK 6mA, CB = total capacitance of one bus line in pF, tR and tF measured between 0.3VVID and 0.7VVID, CB 400pF 0.6 0 50 (Note 4) CONDITIONS MIN 1.3 0.6 0.6 0 100 100 0.9 TYP MAX UNITS s s s s ns ns s ns
Note 1: Note 2: Note 3: Note 4:
All devices are 100% production tested at TA = +25C. Specifications over temperature limits are guaranteed by design. Normal operation mode is the POR state. The settling time is measured from the 50% of the input swing to the 0.1% of the final value of the output. A master device must provide a hold time of at least 300ns for the SDA signal (referred to VIL of the SCL signal) in order to bridge the undefined region of SCL's falling edge.
6
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Low-Power Audio/Video Switch for Dual SCART Connectors
Typical Operating Characteristics
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.)
VIDEO SMALL-SIGNAL GAIN vs. FREQUENCY
MAX9598 toc01
MAX9598
VIDEO SMALL-SIGNAL GAIN FLATNESS vs. FREQUENCY
0.5 0 GAIN FLATNESS (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 NO FILTER GAIN (dB) -20 FILTER
MAX9598 toc02
VIDEO LARGE-SIGNAL GAIN vs. FREQUENCY
0 -10 NO FILTER
MAX9598 toc03 MAX9598 toc09 MAX9598 toc06
10 0 -10 GAIN (dB) -20 FILTER -30 -40 -50 -60 -70 VOUT = 100mVP-P 100k 1M 10M NO FILTER
1.0
10
FILTER -30 -40 -50 -60
-3.5 -4.0 100M
VOUT = 100mVP-P 100k 1M 10M 100M
-70
VOUT = 2VP-P 100k 1M 10M 100M
FREQUENCY (Hz)
FREQUENCY (Hz)
FREQUENCY (Hz)
VIDEO LARGE-SIGNAL GAIN FLATNESS vs. FREQUENCY
MAX9598 toc04
VIDEO CROSSTALK vs. FREQUENCY
-10 VIDEO CROSSTALK (dB) -20 GROUP DELAY (ns) -30 -40 -50 -60 -70 FILTER 20 0 100k 1M 10M 100M 100k NO FILTER 80 60 40
MAX9598 toc05
GROUP DELAY vs. FREQUENCY
120 100
1.0 0.5 0 GAIN FLATNESS (dB) -0.5 -1.0 -1.5 -2.0 -2.5 -3.0 -3.5 -4.0 100k 1M 10M VOUT = 2VP-P NO FILTER FILTER
0
-80 100M FREQUENCY (Hz) FREQUENCY (Hz)
1M
10M
100M
FREQUENCY (Hz)
VVID POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
MAX9598 toc07
VIDEO VOLTAGE GAIN vs. TEMPERATURE
2.04 2.03 VOLTAGE GAIN (V/V) 2.02 2.01 2.00 1.99 1.98 1.97 1.96 1.95 0.5 0 0 20 40 TEMPERATURE (C) 60 80 0 VIN = 1VP-P, 100kHz
MAX9598 toc08
VIDEO OUTPUT VOLTAGE vs. INPUT VOLTAGE
3.5 3.0 OUTPUT VOLTAGE (V) 2.5 2.0 1.5 1.0
0 -5 -10 VVID PSRR (dB) -15 -20 -25 -30 -35 -40 -45 -50
VVID = 3.3V + 100mVP-P
2.05
0.1
1
10
100
0.5
1.0 INPUT VOLTAGE (V)
1.5
2.0
FREQUENCY (MHz)
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7
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.)
DIFFERENTIAL GAIN AND PHASE
DIFFERENTIAL GAIN (%) DIFFERENTIAL GAIN (%)
MAX9598 toc10
DIFFERENTIAL GAIN AND PHASE
0.1 0 -0.1 -0.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 1 2 3 4 2 3 4 f = 4.43MHz, FILTER 5 6 7
MAX9598 toc11
2T RESPONSE
MAX9598 toc12
0.2 0.1 0 -0.1 -0.2 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 1 2 3 2 3 f = 4.43MHz, NO FILTER 4 5 6 7
0.2
INPUT 200mV/div
DIFFERENTIAL PHASE (deg)
DIFFERENTIAL PHASE (deg)
OUTPUT 400mV/div
f = 4.43MHz, NO FILTER 4 5 6 7
f = 4.43MHz, FILTER 5 6 7 100ns/div
12.5T RESPONSE
MAX9598 toc13
NTC-7 VIDEO TEST SIGNAL
MAX9598 toc14
FIELD SQUARE-WAVE RESPONSE
MAX9598 toc15
INPUT 200mV/div
INPUT 0.5V/div
INPUT 500mV/div
OUTPUT 1V/div OUTPUT 400mV/div OUTPUT 1V/div
400ns/div
10s/div
2ms/div
SYNC TIP CLAMP VOLTAGE vs. TEMPERATURE
MAX9598 toc16
BIAS VOLTAGE vs. TEMPERATURE
MAX9598 toc17
INPUT SYNC-TIP CLAMP CURRENT vs. TEMPERATURE
INPUT SYNC-TIP CLAMP CURRENT (A) VIN = 0.3V 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0 25 50 75
MAX9598 toc18
1.0 0.9 SYNC TIP CLAMP VOLTAGE (mV) 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 20 40 TEMPERATURE (C) 60
660 650 640 BIAS VOLTAGE (mV) 630 620 610 600 590 580 570 560 550
1.4
80
0
20
40 TEMPERATURE (C)
60
80
TEMPERATURE (C)
8
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Typical Operating Characteristics (continued)
(VVID = VAUD = 3.3V, V12 = 12V, VGNDVID = VEP = 0V, video load is 150 to GNDVID, audio load is 10k to EP, TA = +25C, unless otherwise noted.)
INPUT CLAMP CURRENT vs. INPUT VOLTAGE
MAX9598 toc19
OUTPUT LEVEL VOLTAGE vs. TEMPERATURE
340 OUTPUT LEVEL VOLTAGE (mV) 330 320 GAIN (V/V) 310 300 290 280 270 260 250 0 0 20 40 TEMPERATURE (C) 60 80 10 1 3
MAX9598 toc20
AUDIO LARGE-SIGNAL FREQUENCY RESPONSE vs. GAIN
MAX9598 toc21
8 7 INPUT CLAMP CURRENT (A) 6 5 4 3 2 1 0 0 0.5 1.0 1.5 2.0 2.5 3.0
350
5
4
2
VIN = 0.25VRMS 100 1k 10k 100k 1M
3.5
INPUT VOLTAGE (V)
FREQUENCY (Hz)
AUDIO CROSSTALK vs. FREQUENCY
VIN = 0.25VRMS RL = 10k TO GNDAUD
MAX9598 toc22
AUDIO TOTAL HARMONIC DISTORTION PLUS NOISE vs. FREQUENCY
MAX9598 toc23
VAUD POWER-SUPPLY REJECTION RATIO vs. FREQUENCY
VAUD = 3.3V + 100mVP-P -20 VAUD PSRR (dB) -40 -60 -80 -100
MAX9598 toc24
0 -20 AUDIO CROSSTALK (dB) -40
1
0
0.1 THD+N (%)
-60 -80
0.01
VIN = 250mVRMS RL = 10k
0.001 -100 -120 10 100 1k FREQUENCY (Hz) 10k 100k 0.0001 10 VIN = 500mVRMS RL = 10k 100 1k FREQUENCY (Hz) 10k 100k
-120 10 100 1k FREQUENCY (Hz) 10k 100k
VVID SUPPLY CURRENT vs. TEMPERATURE
MAX9598 toc25
VAUD SUPPLY CURRENT vs. TEMPERATURE
MAX9598 toc26
V12 SUPPLY CURRENT vs. TEMPERATURE
MAX9598 toc27
40 35 VVID SUPPLY CURRENT (mA) 30 25 20 15 10 5 0 0 20 40 TEMPERATURE (C) 60
6 5 4 3 2 1 0
1000
VAUD SUPPLY CURRENT (mA)
V12 SUPPLY CURRENT (nA) 0 20 40 TEMPERATURE (C) 60 80
800
600
400
200
0 0 20 40 TEMPERATURE (C) 60 80
80
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9
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Pin Description
PIN 1 2 3 4 NAME SDA SCL DEV_ADDR INT I2C Clock Input Device Address Set Input. Connect DEV_ADDR to GNDVID, VVID, SDA or SCL. See Table 3. Interrupt Output. This is an open-drain output that pulls down to GNDVID to indicate a change in the VCR slow-switching input, the activity status of the composite video inputs, or the load status of the composite video outputs. Audio Supply. Connect to a 3.3V supply. Bypass with a 10F aluminum electrolytic capacitor in parallel with a 0.1F ceramic capacitor to EP. Charge-Pump Flying Capacitor Positive Terminal. Connect a 1F capacitor from C1P to C1N. Charge-Pump Flying Capacitor Negative Terminal. Connect a 1F capacitor from C1P to C1N. Charge-Pump Negative Power Supply. Bypass CPVSS with a 1F ceramic capacitor to EP. Encoder Left-Channel Audio Input Encoder Right-Channel Audio Input VCR SCART Left-Channel Audio Input VCR SCART Right-Channel Audio Input TV SCART Left-Channel Audio Output VCR SCART Left-Channel Audio Output VCR SCART Right-Channel Audio Output TV SCART Right-Channel Audio Output TV SCART Bidirectional Slow-Switch Signal +12V Supply. Bypass V12 with a 0.1F capacitor to EP. VCR SCART Bidirectional Slow-Switch Signal TV SCART Fast-Switching Logic Output VCR SCART Fast-Switching Input Encoder Blue Video Input Encoder Green Video Input VCR SCART Blue Video Input VCR SCART Green Video Input TV SCART Blue Video Output TV SCART Green Video Output Video Ground VCR SCART Red/Chroma Video Input Video and Digital Supply. Connect to a +3.3V supply. Bypass with a parallel 1F and 0.1F ceramic capacitor to GNDVID. VVID also serves as a digital supply for the I2C interface. FUNCTION Bidirectional, I2C Data I/O. Output is open drain and tolerates up to 3.6V.
5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
VAUD C1P C1N CPVSS ENC_INL ENC_INR VCR_INL VCR_INR TV_OUTL VCR_OUTL VCR_OUTR TV_OUTR TV_SS V12 VCR_SS TVOUT_FS VCRIN_FS ENC_B_IN ENC_G_IN VCR_B_IN VCR_G_IN TV_B_OUT TV_G_OUT GNDVID VCR_R/C_IN VVID
10
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Low-Power Audio/Video Switch for Dual SCART Connectors
Pin Description (continued)
PIN 31 32 33 34 35 36 37 38 39 40 EP NAME ENC_C_IN ENC_R/C_IN TV_R/C_OUT VCR_R/C_OUT Encoder Chroma Video Input Encoder Red/Chroma Video Input TV SCART Red/Chroma Video Output VCR SCART Red/Chroma Video Output FUNCTION
MAX9598
VCR_Y/CVBS_OUT VCR SCART Luma/Composite Video Output TV_Y/CVBS_OUT VCR_Y/CVBS_IN TV_Y/CVBS_IN ENC_Y_IN ENC_Y/CVBS_IN EP TV SCART Luma/Composite Video Output VCR SCART Luma/Composite Video Input TV SCART Luma/Composite Video Input Encoder Luma Video Input Encoder Luma/Composite Video Input Exposed Pad. The exposed pad is the internal ground for the audio amplifiers and charge pump. A low-impedance connection between ground and EP is required for proper isolation.
Detailed Description
The MAX9598 represents Maxim's third generation of SCART1 audio/video (A/V) switches. Under I2C control, these devices route audio, video, and control information between the set-top box decoder chip and two SCART connectors. The audio signals are left audio and right audio. The video signals are composite video with blanking and sync (CVBS) and component video (red, green, blue). S-video (Y/C) can be transported across the SCART interface if CVBS is reassigned to luma (Y) and red is reassigned to chroma (C). Support for S-video is optional. The slow-switch signal and the fast-switch signal carry control information. The slowswitch signal is a 12V, trilevel signal that indicates whether the picture aspect ratio is 4:3 or 16:9 or causes the television to use an internal A/V source such as an antenna. The fast-switch signal indicates whether the television should display CVBS or RGB signals. CVBS, left audio, and right audio are full duplex. All the other signals are half duplex. Therefore, one device on the link must be designated as the transmitter and the other device must be designated as the receiver.
The low-power consumption and the advanced monitoring functions of the MAX9598 enable the creation of lower power set-top boxes, televisions, and DVD players. Unlike competing SCART ICs, the audio and video circuits of the MAX9598 operate entirely from 3.3V rather than from 5V and 12V. Only the slow-switch circuit of the MAX9598 requires a 12V supply. The MAX9598 also has circuits that detect activity on the CVBS inputs, loads on the CVBS outputs, and the level of the slow-switch signals. The INT signal informs the C if there are any changes so that the C can intelligently decide whether to power up or power down the equipment. In addition, the MAX9598 has DirectDrive audio circuitry to eliminate click-and-pop noise. With DirectDrive, the DC bias of the audio line outputs is always at ground, no matter whether the MAX9598 is being powered up or powered down. Conventional audio line output drivers that operate from a single supply require series AC-coupling capacitors. During power-up, the DC bias on the AC-coupling capacitor moves from ground to a positive voltage, and during power-down, the opposite occurs. The changing DC bias usually causes an audible transient.
1SCART (from Syndicat des Constructeurs d'Appareils Radiorecepteurs et Televiseurs) is a French-originated standard and associated 21-pin connector for connecting audio-visual equipment together. The official standard for SCART is CENELEC document number EN 50049-1. From Wikipedia. ______________________________________________________________________________________ 11
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Audio Section
The audio circuit is essentially a stereo, 2x2, nonblocking, audio crosspoint with output drivers. The encoder (stereo audio DAC) and the VCR are the two input sources, and the two outputs go to the TV SCART connector and the VCR SCART connector. See Figure 1. The integrated charge pump inverts the +3.3V supply to create a -3.3V supply. The audio circuit operates from bipolar supplies so the audio signal is always biased to ground.
MAX9598
ZERO-CROSS DETECTOR
VAUD
EP ENC_INL VCR_INL AV = 4V/V TV_OUTL
VAUD
EP AV = 4V/V VCR_OUTL
ZERO-CROSS DETECTOR
VAUD
EP ENC_INR VCR_INR AV = 4V/V TV_OUTR
VAUD
EP AV = 4V/V VCR_OUTR
VAUD C1P C1N CPVSS
CHARGE PUMP
Figure 1. MAX9598 Audio Section Functional Diagram
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Low-Power Audio/Video Switch for Dual SCART Connectors
Clickless Switching The TV audio channel incorporates a zero-crossing detect (ZCD) circuit that minimizes click noise due to abrupt signal level changes that occur when switching between audio signals at an arbitrary moment. To implement the zero-crossing function when switching audio signals, set the ZCD bit high (Audio Control Register 00h, bit 6). Then set the mute bit high (Audio Control Register, 00h, bit 0). Next, wait for a sufficient period of time for the audio signal to cross zero. This period is a function of the audio signal path's low-frequency 3dB corner (fL3dB). Thus, if fL3dB = 20Hz, the time period to wait for a zero-crossing detect is 1/20Hz or 50ms. After the wait period, select a new audio source for the TV audio channel by writing to bits 1 and 0 of the TV Audio Control Register (01h). Finally, clear mute (Audio Control Register, 00h, bit 0) but leave ZCD (Audio Control Register, 00h, bit 6) high. The MAX9598 switches the signal out of mute at the next zero crossing. See Tables 10 and 11. Audio Outputs The MAX9598 audio output amplifiers feature Maxim's patented DirectDrive architecture, thereby eliminating the need for output-coupling capacitors required by conventional single-supply audio line drivers. An internal charge pump inverts the positive supply (VAUD), creating a negative supply (CPVSS). The audio output amplifiers operate from these bipolar supplies with their outputs biased about audio ground (Figure 2). The benefit of this audio ground bias is that the amplifier outputs do not have a DC component. The DC-blocking capacitors required with conventional audio line drivers are unnecessary, conserving board space, reducing system cost, and improving frequency response. Conventional single-supply audio line drivers have their outputs biased about a nominal DC voltage (typically half the supply) for maximum dynamic range. Large coupling capacitors are needed to block this DC bias. Clicks and pops are created when the coupling capacitors are charged during power-up and discharged during power-down. The MAX9598 features a low-noise charge pump that requires only two small ceramic capacitors. The 580kHz switching frequency is well beyond the audio range and does not interfere with audio signals. The switch drivers feature a controlled switching speed that minimizes noise on the video outputs generated by turn-on and turn-off transients.
MAX9598
VDD VOUT VDD/2 GND
CONVENTIONAL DRIVER-BIASING SCHEME
+VDD
VOUT
GND
-VDD
DirectDrive BIASING SCHEME
Figure 2. Conventional Driver Output Waveform vs. MAX9598 Output Waveform
The SCART standard specifies 2VRMS as the full-scale for audio signals. As the audio circuits process 0.5V RMS full-scale audio signals internal to the MAX9598, the gain-of-4 output amplifiers restore the audio signals to a full scale of 2VRMS. To select which audio input source is routed to the TV SCART connector, write to bits 1 and 0 of the TV Audio Control Register (01h). To select which audio input source is routed to the VCR SCART connector, write to bits 3 and 2 of the TV Audio Control Register (01h). The power-on default is for the TV and VCR audio outputs to be muted (the inputs of the output amplifiers are connected to audio ground). See Tables 8 and 11.
Video Section
The video circuit routes different video formats between the set-top box decoder, the TV SCART connector, and the VCR SCART connector. It also routes slow-switch and fast-switch control information. See Figure 3.
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT ACTIVITY DETECT TV_Y/CVBS_IN VCR_Y/CVBS_IN ENC_Y/CVBS_IN ENC_Y_IN CLAMP CLAMP AV = 2V/V CLAMP CLAMP MUTE LOAD SENSE AV = 2V/V VCR_Y/CVBS_OUT LPF LPF TV_Y/CVBS_OUT LOAD SENSE
MAX9598
VCR_R/C_IN ENC_R/C_IN ENC_C_IN
CLAMP/BIAS AV = 2V/V CLAMP/BIAS CLAMP/BIAS MUTE AV = 2V/V VCR_R/C_OUT LPF LPF TV_R/C_OUT
VCR_G_IN ENC_G_IN
CLAMP AV = 2V/V CLAMP MUTE LPF TV_G_OUT
VCR_B_IN ENC_B_IN
CLAMP AV = 2V/V CLAMP MUTE VVID AV = 1V/V GNDVID TVOUT_FS LPF TV_B_OUT
VCRIN_FS 0.7V V12 AV = 1V/V +6V EP TO I2C x1 V12 AV = 1V/V +6V EP TO I2C x1 VCR_SS TV_SS
Figure 3. MAX9598 Video Section Functional Diagram
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Low-Power Audio/Video Switch for Dual SCART Connectors
Video Inputs Whether the incoming video signal is AC-coupled or DC-coupled into the MAX9598 depends upon the origin, format, and voltage range of the video signal. Table 1 below shows the recommended connections. Always AC-couple an external video signal through a 0.1F capacitor because its voltage is not well defined (see the Typical Application Circuit). For example, the video transmitter circuit might have a different ground than the video receiver, thereby level shifting the DC bias. The 60Hz power line "hum" might cause the video signal to slowly change DC bias. Internal video signals that are between 0 and 1V can be DC-coupled. Most video DACs generate video signals between 0 and 1V because the video DAC sources current into a ground-referenced resistor. For the minority of video DACs that generate video signals between 2.3V and 3.3V because the video DAC sinks current from a VVID-referenced resistor, AC-couple the video signal to the MAX9598.
The MAX9598 restores the DC level of incoming, ACcoupled video signals with either transparent sync-tip clamps or bias circuits. When using an AC-coupled input, the transparent sync-tip clamp automatically clamps the input signal minimum to ground, preventing it from going lower. A small current of 1A pulls down on the input to prevent an AC-coupled signal from drifting outside the input range of the part. Use sync-tip clamps with CVBS, RGB, and luma signals. The transparent sync-tip clamp is "transparent" when the incoming video signal is DC-coupled and at or above ground. Under such conditions, the clamp never activates. Therefore, the outputs of video DACs that typically generate signals between 0 and 1V can be directly connected to the MAX9598 inputs. The bias circuit accepts AC-coupled chroma, which is a subcarrier with the color information modulated onto it. The bias voltage of the bias circuits is 600mV. ENC_R/C_IN and VCR_R/C_IN can receive either a red video signal or a chroma video signal. Set the input configuration by writing to bits 7 and 3 of the VCR Video Input Control Register (08h). See Tables 8 and 14. The MAX9598 also has video input detection. When activated, activity detect circuits check if sync is present on incoming CVBS signals. If so, then there is a valid video signal. Read bits 0, 2, 4, and 5 of the Video Activity Status Register (0Fh) to determine the status of the CVBS inputs. See Table 19.
MAX9598
Video Reconstruction Filter The video DAC outputs of the set-top box decoder chip need to be lowpass-filtered to reject the out-of-band noise. The MAX9598 integrates 6th-order, Butterworth filters. The filter passband (1dB) is typically 10MHz, and the attenuation at 27MHz is 52dB. The filters are suited for standard-definition video. Video Outputs The video output amplifiers can both source and sink load current, allowing output loads to be DC- or AC-coupled. The amplifier output stage needs around 300mV of headroom from either supply rail. For video signals with a sync pulse, the sync tip will typically be at 300mV, as shown in Figure 4. For a chroma signal, the blank level will typically be at 1.5V, as shown in Figure 5.
Table 1. Recommended Coupling for Incoming Video Signals and Input Circuit Configuration. (Use a 0.1F Capacitor to AC-Couple a Video Signal into the MAX9598)
VIDEO ORIGIN External External External External Internal Internal Internal Internal Internal Internal Internal Internal FORMAT CVBS RGB Y C CVBS R, G, B Y, C Y, Pb, Pr CVBS R, G, B Y C VOLTAGE RANGE (V) Unknown Unknown Unknown Unknown 0 to 1 0 to 1 0 to 1 0 to 1 2.3 to 3.3 2.3 to 3.3 2.3 to 3.3 2.3 to 3.3 COUPLING AC AC AC AC DC DC DC DC AC AC AC AC INPUT CIRCUIT CONFIGURATION Transparent Sync Tip Clamp Transparent Sync Tip Clamp Transparent Sync Tip Clamp Bias Circuit Transparent Sync Tip Clamp Transparent Sync Tip Clamp Transparent Sync Tip Clamp Transparent Sync Tip Clamp Transparent Sync Tip Clamp Transparent Sync Tip Clamp Transparent Sync Tip Clamp Bias Circuit
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
MAX9598 fig04 MAX9598 fig05
500mV/div
500mV/div
0V
0V
10s/div
20s/div
Figure 4. MAX9598 Video Output with CVBS Signal (Multiburst Video Test Signal Shown)
Figure 5. MAX9598 Video Output with Chroma (C) Signal (75% Color Bar Video Test Signal Shown)
If the supply voltage is greater than 3.135V (5% below a 3.3V supply), each amplifier can drive two DC-coupled video loads to ground. If the supply is less than 3.135V, each amplifier can drive only one DC-coupled or AC-coupled video load. The SCART standard allows for video signals to have a superimposed DC component within 0 to 2V. Therefore, most video signals are DC-coupled at the output. In the unlikely event that the video signal needs to be ACcoupled, the coupling capacitors should be 220F or greater in order to keep the highpass filter formed by the 37.5 equivalent resistance of the video transmission line to a corner frequency of 4.8Hz or below in order to keep it well below the 25Hz frame rate of the PAL standard. The CVBS outputs have load sense circuits. If enabled, each load sense circuit checks for a load eight times per second by connecting an internal 15k pullup resistor to the output for 1ms. If the output is pulled up, then no load is present. If the output stays low, then a load is connected. Read bits 1 and 3 to determine load status. See Table 19. The selection of video sources that are sent to the TV SCART connector are controlled by bits 0 to 4 of the TV Video Input Control Register (06h) while the selection of video sources that are sent to the VCR SCART connector are controlled by bits 0 to 2 of the VCR Video Input Control Register (08h). See Tables 8, 12, and 14. The video outputs can be enabled or disabled by bits 2 to 7 of the Output Enable Register (0Dh). See Table 16.
Slow Switching The MAX9598 supports the IEC 933-1, Amendment 1, trilevel slow switching that selects the aspect ratio for the display (TV). Under I2C control, the MAX9598 sets the slow-switching output voltage level. Table 2 shows the valid input levels of the slow-switching signal and the corresponding operating modes of the display device.
Two bidirectional ports are available for slow-switching signals for the TV and VCR. The slow-switching input status is continuously read and stored in the Status Register (0Eh). The slow-switching outputs can be set to a logic level or high impedance by writing to the TV Video Output Control Register (07h) and the VCR Video Output Control Register (09h). When enabled, INT becomes active low if the voltage level changes on TV_SS or VCR_SS. See Tables 8, 13, 15 and 18.
Table 2. Slow-Switching Modes
SLOW-SWITCHING SIGNAL VOLTAGE (V) 0 to 2 MODE Display device uses an internal source such as a built-in tuner to provide a video signal Display device uses a video signal from the SCART connector and sets the display to 16:9 aspect ratio Display device uses a signal from the SCART connector and sets the display to 4:3 aspect ratio
4.5 to 7.0
9.5 to 12.6
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Low-Power Audio/Video Switch for Dual SCART Connectors
Fast Switching The fast-switching signal was originally used to switch between CVBS and RGB signals on a pixel-by-pixel basis so that on-screen display (OSD) information could be inserted. Since modern set-top box decoder chips have integrated OSD circuitry, there is no need to create OSD information using the older technique. Now, the fast-switching signal is just used to switch between CVBS and RGB signal sources. Set the source of the fast-switching signal by writing to bits 4 and 3 of the TV Video Output Control Register (07h). The fast switching signal to the TV SCART connector can be enabled or disabled by bit 1 of the Output Enable Register (0Dh). See Tables 8, 13, and 16.
edge clock pulse. A master reads from the MAX9598 by transmitting the slave address with the R/W bit set to 0, the register address of the register to be read, a REPEATED START (Sr) condition, the slave address with the R/W bit set to 1, followed by a series of SCL pulses. The MAX9598 transmits data on SDA in sync with the master-generated SCL pulses. The master acknowledges receipt of each byte of data. Each read sequence is framed by a START (S) or REPEATED START (Sr) condition, an acknowledge or a not acknowledge, and a STOP (P) condition. SDA operates as both an input and an open-drain output. A pullup resistor, typically greater than 500, is required on the SDA bus. SCL operates as only an input. A pullup resistor, typically greater than 500, is required on SCL if there are multiple masters on the bus, or if the master in a singlemaster system has an open-drain SCL output. Series resistors in line with SDA and SCL are optional. Series resistors protect the digital inputs of the MAX9598 from high-voltage spikes on the bus lines, and minimize crosstalk and undershoot of the bus signals.
MAX9598
I2C Serial Interface
The MAX9598 features an I2C/SMBusTM-compatible, 2wire serial interface consisting of a serial data line (SDA) and a serial clock line (SCL). SDA and SCL facilitate communication between the MAX9598 and the master at clock rates up to 400kHz. Figure 6 shows the 2-wire interface timing diagram. The master generates SCL and initiates data transfer on the bus. A master device writes data to the MAX9598 by transmitting a START (S) condition, the proper slave address with the R/W bit set to 0, followed by the register address and then the data word. Each transmit sequence is framed by a START (S) and a STOP (P) condition. Each word transmitted to the MAX9598 is 8 bits long and is followed by an acknowl-
Bit Transfer One data bit is transferred during each SCL cycle. The data on SDA must remain stable during the high period of the SCL pulse. Changes in SDA while SCL is high are control signals (see the START and STOP Conditions section). SDA and SCL idle high when the I2C bus is not busy.
SDA tSU, DAT tLOW SCL tHD, STA tR START CONDITION tHIGH tF REPEATED START CONDITION STOP CONDITION START CONDITION tHD, DAT tSU, STA tBUF tSU, STA tSP tSU, STO
Figure 6. I2C Serial-Interface Timing Diagram
SMBus is a trademark of Intel Corporation.
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Low-Power Audio/Video Switch for Dual SCART Connectors
START and STOP Conditions SDA and SCL idle high when the bus is not in use. A master initiates communication by issuing a START condition. A START condition is a high-to-low transition on SDA with SCL high. A STOP condition is a low-to-high transition on SDA while SCL is high (Figure 7). A START condition from the master signals the beginning of a transmission to the MAX9598. The master terminates transmission, and frees the bus, by issuing a STOP condition. The bus remains active if a REPEATED START condition is generated instead of a STOP condition. Early STOP Conditions The MAX9598 recognizes a STOP condition at any point during data transmission except if the STOP condition occurs in the same high pulse as a START condition. For proper operation, do not send a STOP condition during the same SCL high pulse as the START condition. Slave Address The slave address is defined as the 7 MSBs (most significant bits) followed by the R/W (read/write) bit. Set the R/W bit to 1 to configure the MAX9598 to read mode. Set the R/W bit to 0 to configure the MAX9598 to
MAX9598
write mode. The slave address is always the first byte of information sent to the MAX9598 after a START or a REPEATED START condition. The MAX9598 slave address is configurable with DEV_ADDR. Table 3 shows the possible slave addresses for the MAX9598.
Acknowledge The acknowledge bit (ACK) is a clocked 9th bit that the MAX9598 uses to handshake receipt of each byte of data when in write mode (see Figure 8). The MAX9598 pulls down SDA during the entire master-generated 9th clock pulse if the previous byte is successfully received. Monitoring ACK allows for detection of unsuccessful data transfers. An unsuccessful data transfer occurs if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master may retry communication. The master pulls down SDA during the 9th clock cycle to acknowledge receipt of data when the MAX9598 is in read mode. An acknowledge is sent by the master after each read byte to allow data transfer to continue. A not acknowledge is sent when the master reads the final byte of data from the MAX9598, followed by a STOP condition.
S
Sr
P
START CONDITION
CLOCK PULSE FOR ACKNOWLEDGMENT
SCL
SCL 1 2 8 NOT ACKNOWLEDGE 9
SDA
SDA ACKNOWLEDGE
Figure 7. START, STOP, and REPEATED START Conditions
Figure 8. Acknowledge
Table 3. Slave Address
DEV_ADDR GNDVID VVID SCL SDA B7 1 1 1 1 B6 0 0 0 0 B5 0 0 0 0 B4 1 1 1 1 B3 0 0 1 1 B2 1 1 0 0 B1 0 1 0 1 B0 R/W R/W R/W R/W WRITE ADDRESS (hex) 94h 96h 98h 9Ah READ ADDRESS (hex) 95h 97h 99h 9Bh
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Low-Power Audio/Video Switch for Dual SCART Connectors
Write Data Format A write to the MAX9598 consists of transmitting a START condition, the slave address with the R/W bit set to 0, one data byte to configure the internal register address pointer, 1 or more data bytes, and a STOP condition. Figure 9 illustrates the proper frame format for writing 1 byte of data to the MAX9598. Figure 10 illustrates the frame format for writing n bytes of data to the MAX9598. The slave address with the R/W bit set to 0 indicates that the master intends to write data to the MAX9598. The MAX9598 acknowledges receipt of the address byte during the master-generated ninth SCL pulse. The second byte transmitted from the master configures the MAX9598's internal register address pointer. The pointer tells the MAX9598 where to write the next byte of data. An acknowledge pulse is sent by the MAX9598 upon receipt of the address pointer data. The third byte sent to the MAX9598 contains the data that will be written to the chosen register. An acknowledge pulse from the MAX9598 signals receipt of the data byte. The address pointer autoincrements to the next register address after each received data byte. This autoincrement feature allows a master to write to sequential register address locations within one continuous frame. The master signals the end of transmission by issuing a STOP condition. Read Data Format The master presets the address pointer by first sending the MAX9598's slave address with the R/W bit set to 0 followed by the register address after a START condition. The MAX9598 acknowledges receipt of its slave address and the register address by pulling SDA low during the ninth SCL clock pulse. A REPEATED START condition is then sent followed by the slave address with the R/W bit set to 1. The MAX9598 transmits the contents of the specified register. Transmitted data is valid on the rising edge of the master-generated serial clock (SCL). The address pointer autoincrements after each read data byte. This autoincrement feature allows all registers to be read sequentially within one continuous frame. A STOP condition can be issued after any number of read data bytes. If a STOP condition is issued followed by another read operation, the first data byte to be read will be from the register address location set by the previous transaction and not 00h and subsequent reads will autoincrement the address pointer until the next STOP condition. Attempting to read from register addresses higher than 01h results in repeated reads from a dummy register containing FFh data. The master acknowledges receipt of each read byte during the acknowledge clock pulse. The master must acknowledge all correctly received bytes except the last byte. The final byte must be followed by a not acknowledge from the master and then a STOP condition. Figures 11 and 12 illustrate the frame format for reading data from the MAX9598.
ACKNOWLEDGE FROM MAX9598 B7 ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9598 REGISTER ADDRESS A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P B6 B5 B4 B3 B2 B1 B0
MAX9598
Figure 9. Writing a Byte of Data to the MAX9598
ACKNOWLEDGE FROM MAX9598 ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9598 REGISTER ADDRESS A B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE 1 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A
ACKNOWLEDGE FROM MAX9598 B7 B6 B5 B4 B3 B2 B1 B0 DATA BYTE n 1 BYTE A P
Figure 10. Writing n Bytes of Data to the MAX9598
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
NOT ACKNOWLEDGE FROM MASTER ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS R/W 0 A ACKNOWLEDGE FROM MAX9598 REGISTER ADDRESS A ACKNOWLEDGE FROM MAX9598 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 11. Reading 1 Indexed Byte of Data from the MAX9598
ACKNOWLEDGE FROM MAX9598 S SLAVE ADDRESS R/W 0 A
ACKNOWLEDGE FROM MAX9598 REGISTER ADDRESS A
ACKNOWLEDGE FROM MAX9598 Sr SLAVE ADDRESS R/W 1 A DATA BYTE 1 BYTE AUTOINCREMENT INTERNAL REGISTER ADDRESS POINTER A P
REPEATED START
Figure 12. Reading n Bytes of Indexed Data from the MAX9598
Interrupt Output
When interrupt is enabled in modes 1 and 2 (see the Operating Modes section), INT, which is an open-drain output, pulls low under the following conditions: slowswitch signals change value, CVBS input signals are detected or disappear, and CVBS output loads are added or removed. When interrupt is enabled in mode 3, INT pulls low only when the slow-switch signal changes value. Enable INT by writing a 1 into bit 4 of register 01h. See Table 11. The interrupt can be cleared by reading register 0Eh and 0Fh.
STEREO AUDIO DACS 1F 6.65k ENC_INL R1* 1F 6.65k ENC_INR R1*
MAX9598
Applications Information
Audio Inputs The maximum full-scale audio signal that can be applied to the audio inputs is 0.5V RMS biased at ground. The recommended application circuit to attenuate and bias an incoming audio signal is shown in Figure 13. The audio path has a gain of 4V/V so that the full scale of the audio output signal is 2VRMS. If less than 2VRMS full scale is desired at the audio outputs, then the full scale of the audio input signal should be proportionately decreased below 0.5VRMS.
*R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1%
Figure 13. Application Circuit to Connect Audio Source to Audio Inputs (1F Capacitor Connected to the Ground-Referenced Resistors Biases the Audio Signal at Ground, Resistors Attenuate the Audio Signal)
Operating Modes
The MAX9598 has four operating modes, which can be set by writing to bits 6 and 7 of register 10h. See Table 17.
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 4. Register Settings for Looping VCR Signals to the TV
DESCRIPTION REGISTER 00h 01h 06h Loop VCR signals to the TV 07h 08h 09h 0Dh 10h 0 0 0 x 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 0 BIT 7 6 5 4 1 0 1 0 0 1 0 3 1 1 0 x 0 1 0 2 1 0 0 1 1 1 0 1 0 1 x 1 1 1 0 0 1 0 x 1 0 1 0 (Note 5) (Note 6) Default COMMENTS
Note 5: TV slow-switch output (bits 1 and 0) should be the same as VCR slow-switch input. Note 6: User has to set bits 7 and 3 appropriately depending upon whether signal is red or chroma.
Shutdown All circuitry is shut down in the MAX9598 except for the I2C interface, which is designed with static CMOS logic. Except for register 10h, which sets the operating mode, the values in all the other I2C registers are preserved while entering, during, and leaving shutdown mode. Low-Power Mode Put the MAX9598 into low-power mode during standby. Everything is shut down except for the slow-switching circuits, CVBS input detection, CVBS load detection, and I2C interface. If interrupt is enabled, then INT will go active low whenever the slow-switch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The C in the set-top box can then decide whether to change the MAX9598 to fullpower mode and loop VCR signals to the TV. Before entering low-power mode, the slow-switch signals should be set to high impedance.
Except for registers 0Eh, 0Fh, and 10h, the value in all of the other I2C registers are preserved while entering, during, and leaving low-power mode. The values in registers
0Eh and 0Fh might change in low-power mode because they provide status on the slow switch signals, CVBS input, and CVBS outputs. The value in register 10h changes while entering or leaving low-power mode because bits 6 and 7 set the operating mode. Full-Power Mode with Video Input Detection and Video Load Detection In this mode, the MAX9598 is fully on. If interrupt is enabled, then INT will go active low whenever the slowswitch signal changes; a CVBS signal appears or disappears; or a CVBS load appears or disappears. The C can decide whether to change the routing configuration or operating mode of the MAX9598.
Full-Power Mode Without Video Input Detection and Video Load Detection This mode is similar to the above mode except that video input detection and video load detection are not active. If interrupt is enabled, then INT will go active low only when the slow-switch signal changes.
Table 5. Quiescent Power Consumption
OPERATING MODE Shutdown. Low-power mode with slow switching, CVBS input video detection, and video load detection active only. Audio circuitry is off. Full-power mode WITH input video detection and video load detection active. Full-power mode WITHOUT input video detection and video load detection active (power-on default). POWER CONSUMPTION (mW) 0.1 1.7
71 70
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 6. Average Power Consumption
OPERATING MODE Full-power mode WITH input video detection and video load detection active. Full-power mode WITHOUT input video detection and video load detection active (power-on default). POWER CONSUMPTION (mW) 471 470
Table 7. Conditions for Average Power Consumption Measurement
PIN 5 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 NAME VAUD ENC_INL ENC_INR VCR_INL VCR_INR TV_OUTL VCR_OUTL VCR_OUTR TV_OUTR TV_SS V12 VCR_SS TVOUT_FS VCRIN_FS ENC_B_IN ENC_G_IN VCR_B_IN VCR_G_IN TV_B_OUT TV_G_OUT GNDVID VCR_R/C_IN VVID ENC_C_IN ENC_R/C_IN TV_R/C_OUT VCR_R/C_OUT VCR_Y/CVBS_OUT TV_Y/CVBS_OUT VCR_Y/CVBS_IN TV_Y/CVBS_IN ENC_Y_IN ENC_Y/CVBS_IN TYPE Supply Input Input Input Input Output Output Output Output Output Supply Input Output Input Input Input Input Input Output Output Supply Input Supply Input Input Output Output Output Output Input Input Input Input SIGNAL 3.3V 0.25VRMS, 1kHz 0.25VRMS, 1kHz None None 1VRMS, 1kHz 1VRMS, 1kHz 1VRMS, 1kHz 1VRMS, 1kHz 12V 12V 0 3.3V 0 50% flat field 50% flat field None None 50% flat field 50% flat field 0 None 3.3V None 50% flat field 50% flat field 50% flat field 50% flat field 50% flat field None None None 50% flat field LOAD N/A N/A N/A N/A N/A 10k to ground 10k to ground 10k to ground 10k to ground 10k to ground N/A N/A 150 to ground N/A N/A N/A N/A N/A 150 to ground 150 to ground N/A N/A N/A N/A N/A 150 to ground 150 to ground 150 to ground 150 to ground N/A N/A N/A N/A
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Low-Power Audio/Video Switch for Dual SCART Connectors
Power Consumption
The quiescent power consumption and average power consumption of the MAX9598 are very low because of 3.3V operation and low-power circuit design. Quiescent power consumption is defined when the MAX9598 is operating without loads and without any audio or video signals. Table 5 shows the quiescent power consumption in all four operating modes. Average power consumption is defined when the MAX9598 drives typical signals into typical loads. Table 6 shows the average power consumption in full-power mode and Table 7 shows the input and output conditions. nal. The pins that can carry both CVBS and luma have Y/CVBS in their names, and the pins that can carry red and chroma have R/C in their names. Now, the Y/CVBS signals are full duplex while the R/C signals are half duplex. Therefore, S-video is limited to being half duplex. The MAX9598 has to transmit a chroma signal and receive a chroma signal on the same SCART pin, but not at the same time. The 75 resistor connected to VCR_R/C_OUT must act as a back termination resistor when the MAX9598 is transmitting chroma signal and as an input termination resistor when it is receiving a chroma signal. Figure 14 shows how the MAX9598 transmits a chroma signal to the VCR SCART connector while Figure 15 shows how the MAX9598 receives a chroma from the VCR SCART connector. Write a 0 into bit 2 of register 09h to open the pulldown switch at VCR_R/C_OUT. To close the pulldown switch, write a 0 into bit 6 of register 0Dh to turn off the output amplifier, and then write a 1 into bit 2, register 09h. See Tables 15 and 16.
MAX9598
S-Video
The MAX9598 supports S-video from the set-top box to the TV, set-top box to the VCR, and VCR to the set-top box. S-video was not included in the original SCART specifications but was added afterwards. As a consequence, the luma (Y) signal of S-video shares the same SCART pin as the CVBS signal. Likewise, the chroma (C) signal shares the same SCART pin as the red sig-
0.1F
VCR_R/C_IN ENC_R/C_IN ENC_C_IN
BIAS AV = 2V/V BIAS BIAS LPF LPF
TV_R/C_OUT
75
TV SCART
AV = 2V/V
VCR_R/C_OUT
75
MAX9598
ON
VCR SCART
Figure 14. Gain-of-2 Amplifier on VCR_R/C_OUT Outputs Chroma Signal to VCR SCART Connector (Note the Pulldown Switch on VCR_R/C_OUT Is Open)
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23
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
0.1F VCR_R/C_IN ENC_R/C_IN ENC_C_IN
BIAS AV = 2V/V BIAS BIAS LPF LPF
TV_R/C_OUT
75
TV SCART
AV = 2V/V
VCR_R/C_OUT
75
MAX9598
OFF
VCR SCART
Figure 15. VCR_R/C_IN Receives a Chroma Signal from the VCR SCART Connector. Notice that the Pulldown Switch on VCR_R/C_OUT Is Closed and that the Gain-of-2 Amplifier is Off. The Chroma Signal from VCR SCART IS Looped Through to the TV SCART in the Above Configuration.
TV_OUTR 10k
MAX9598
MONO AUDIO 10k
TV_OUTL 75 TV_Y/CVBS_OUT 75 OR GREATER
TV SCART
75 OR GREATER
RF MODULATOR
Figure 16. Application Circuit to Connect CVBS and Mono Audio from TV SCART to RF Modulator
Interfacing to an RF Modulator
If the set-top box modulates CVBS and mono audio onto an RF carrier (for example, channel 3), then a simple application circuit can provide the needed signals (see Figure 16). A 10k resistor summer circuit between TV_OUTR and TV_OUTL creates the mono audio signal. The resistor-divider to ground on TV_Y/CVBS_OUT creates a video signal with normal amplitude. The unique feature of the MAX9598 that facilitates this application circuit is that the audio and video output amplifiers of
the MAX9598 can drive multiple loads if VAUD and VVID are both greater than 3.135V.
Floating-Chassis Discharge Protection and ESD
Some set-top boxes have a floating chassis problem in which the chassis is not connected to earth ground. As a result, the chassis can charge up to 500V. When a SCART cable is connected to the SCART connector, the charged chassis can discharge through a signal pin. The equivalent circuit is a 2200pF capacitor charged to
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
12V +3.3V 0.1F 3.3V 0.1F 3.3V 0.1F VAUD STB CHIP SDA C SCL INT 75 TV_SS 75 DEV_ADDR TV_B_OUT 75 TV_G_OUT 75 TV_R/C_OUT 75 TVOUT_FS 75 VIDEO ENCODER 75 ENC_Y/CVBS_IN 75 GNDVID 75 ENC_R/C_IN 75 75 ENC_G_IN 75 75 ENC_B_IN 75 VCR_INL 75 ENC_Y_IN 75 VCR_SS 75 ENC_C_IN 75 75 VCR_B_IN VVID GNDVID 75 VCR_G_IN 75 0.1F 75 VCR SCART VVID 0.1F EP 2.55k 75 CPVSS V12 7.68k VCR_OUTL VAUD 1F CPVSS 7.68k VCR_INR 2.55k 75 VAUD VCR_OUTR VAUD 1F CPVSS GNDVID 75 TV_Y/CVBS_IN 75 VAUD TV_Y/CVBS_OUT VVID 75 0.1F GNDVID 75 V12 VVID VAUD TV_OUTR 75 VAUD CPVSS V12 CPVSS VVID EP VVID GNDVID VVID GNDVID VVID GNDVID VVID GNDVID TV SCART
MAX9598
TV_OUTL
CPVSS
GNDVID VVID 75 VCR_R/C_IN VVID 0.1F
GNDVID 75 VCR_R/C_OUT STEREO AUDIO DAC VVID
GNDVID 1F VCRIN_FS 6.65k ENC_INL R1* 1F VCR_Y/CVBS_OUT 6.65k ENC_INR 75 R1* C1P EP C1N VCR_Y/CVBS_IN CPVSS 1F 1F GNDVID 75 VVID 0.1F GNDVID 75 75 GNDVID VVID
*R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1%
Figure 17. Application Circuit to Connect Series Resistors and External ESD Protection Diodes at MAX9598 Outputs
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Low-Power Audio/Video Switch for Dual SCART Connectors
311V connected through less than 0.1 to a signal pin. The MAX9598 is soldered on the PCB when it experiences such a discharge. Therefore, the current spike flows through both external and internal ESD protection devices and is absorbed by the supply bypass capacitors, which have high capacitance and low ESR. To better protect the MAX9598 against excess voltages during the cable discharge condition or ESD events, add series resistors to all inputs and outputs to the SCART connector if series resistors are not already present in the application circuit. Also add external ESD protection diodes (for example, BAV99) on all inputs and outputs to the SCART connector.
MAX9598
with a 10F electrolytic capacitor in parallel with a 0.1F ceramic capacitor to audio ground. Bypass each VVID to video ground with a 0.1F ceramic capacitor.
Power-Supply Bypassing
The MAX9598 features single 3.3V and 12V supply operation and requires no negative supply. The 12V supply, V12 is for the SCART switching function. For V12, place a 0.1F bypass capacitor as close as possible. Connect all VAUD pins together to 3.3V and bypass
Using a Digital Supply The MAX9598 was designed to operate from noisy digital supplies. The high PSRR (49dB at 100kHz) allows the MAX9598 to reject the noise from the digital power supplies (see the Typical Operating Characteristics). If the digital power supply is very noisy and stripes appear on the television screen, increase the supply bypass capacitance. An additional, smaller capacitor in parallel with the main bypass capacitor can reduce digital supply noise because the smaller capacitor has lower equivalent series resistance (ESR) and equivalent series inductance (ESL).
Layout and Grounding
For optimal performance, use controlled-impedance traces for video signal paths and place input termination resistors and output back-termination resistors
Table 8. Data Format for Write Mode
REGISTER ADDRESS (HEXADECIMAL) 00h BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 TV audio output mute TV audio selection
Not used
ZCD Interrupt enable
Not used
01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah 0Bh 0Ch 0Dh 10h
Not used
Not used
Not used
VCR audio selection
Not used Not used Not used Not used Not used Not used VCR_R/C_IN Clamp Not used Not used Not used Not used Not used Not used Not used Not used TV G and B video switch Set TV fast switching Not used Not used Not used Not used Not used VCR_Y/CV BS_OUT enable VCR_R/C_ OUT enable TV_R/C_ OUT enable TV_G_OUT enable TV_B_OUT enable TV_Y/CVBS_ OUT enable TVOUT_FS enable Not used ENC_R/C_IN clamp Not used TV video switch Not used Set TV slow switching
VCR video switch VCR_R/C_ OUT ground Set VCR slow switching
Operating mode
Not used
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 9. Data Format for Read Mode
REGISTER ADDRESS (HEXADECIMAL) 0Eh BIT 7 BIT 6 Power-on reset BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0
Not used
Not used ENC_Y_IN input video detection ENC_Y/CVBS_IN input video detection
VCR slow-switch input status
TV slow-switch input status TV CVBS input video detection
0Fh
Not used
VCR CVBS VCR CVBS TV CVBS input video output load output load detection
Table 10. Register 00h: Audio Control
DESCRIPTION TV Audio Mute Zero-Crossing Detector 0 1 BIT 7 6 5 4 3 2 1 0 0 1 Off On (power-on default) Off On (power-on default) COMMENTS
Table 11. Register 01h: TV Audio Control
DESCRIPTION BIT 7 6 5 4 3 2 1 0 Input Source for TV Audio 0 1 1 0 Input Source for VCR Audio 0 1 1 Interrupt Enable 0 1 0 1 0 1 0 0 1 0 1 Encoder audio VCR audio Not used Mute (power-on default) Encoder audio VCR audio Not used Mute (power-on default) Disabled (power-on default) Enabled COMMENTS
close to the MAX9598. Avoid routing video traces parallel to high-speed data lines. The MAX9598 provides separate ground connections for video and audio supplies. For best performance, use separate ground planes for each of the ground returns and connect all ground planes together at a single point. Refer to the MAX9598 Evaluation Kit for a proven PCB layout example.
If the MAX9598 is mounted using flow soldering or wave soldering, the ground via(s) for the exposed pad should have a finished hole size of at least 14 mils to ensure adequate wicking of soldering onto the exposed pad. If the MAX9598 is mounted using solder mask technique, the via requirement does not apply. In either case, a good connection between the exposed pad and ground is required in order to minimize noise from coupling onto the outputs.
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 12. Register 06h: TV Video Input Control
DESCRIPTION BIT 7 6 5 4 3 2 0 0 0 Input Sources for TV Video 0 1 1 1 1 0 Input Sources for TV_G_OUT and TV_B_OUT 0 1 1 0 1 0 1 1 0 0 1 1 0 0 1 1 0 TV_Y/CVBS_OUT 0 1 0 1 0 1 0 1 ENC_Y/CVBS_IN ENC_Y_IN VCR_Y/CVBS_IN TV_Y/CVBS_IN Not used Mute Mute Mute (power-on default) TV_G_OUT ENC_G_IN VCR_G_IN Mute Mute (power-on default) COMMENTS TV_R/C_OUT ENC_R/C_IN ENC_C_IN VCR_R/C_IN MUTE Not used Mute Mute Mute (power-on default) TV_B_OUT ENC_B_IN VCR_B_IN Mute Mute (power-on default)
Table 13. Register 07h: TV Video Output Control
DESCRIPTION BIT 7 6 5 4 3 2 1 0 Set TV Slow Switching 0 1 1 0 Set TV Fast Switching 0 1 1 0 1 0 1 0 0 1 0 1 COMMENTS Low (< 2V). Internal source (power-on default). Medium (4.5V to 7V). External SCART source with 16:9 aspect ratio. High impedance High (> 9.5V). External SCART source with 4:3 aspect ratio. GNDVID (power-on default) Not used Same level as VCR_FB_IN VVID
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 14. Register 08h: VCR Video Input Control
DESCRIPTION BIT 7 6 5 4 3 2 0 0 0 Input Sources for VCR Video 0 1 1 1 1 ENC_R/C_IN Clamp/Bias VCR_R/C_IN Clamp/Bias 0 1 0 1 1 0 0 1 1 0 0 1 1 0 VCR_Y/CVBS_OUT 0 1 0 1 0 1 0 1 ENC_Y/CVBS_IN ENC_Y_IN VCR_Y/CVBS_IN TV_Y/CVBS_IN Not used Mute Mute Mute (power-on default) COMMENTS VCR_R/C_OUT ENC_R/C_IN ENC_C_IN VCR_R/C_IN MUTE Not used Mute Mute Mute (power-on default)
DC restore clamp active at input (power-on default) Chrominance bias applied at input DC restore clamp active at input (power-on default) Chrominance bias applied at input
Table 15. 09h: VCR Video Output Control
DESCRIPTION BIT 7 6 5 4 3 2 1 0 0 Set VCR Function Switching 1 1 0 VCR_R/C_OUT Ground 1 Ground. Pulldown on TV_R/C_OUT is on, the output amplifier driving VCR_R/C_OUT turns off. 0 0 1 0 1 COMMENTS Low (< 2V). Internal source (power-on default) Medium (4.5V to 7V). External SCART source with 16:9 aspect ratio. High impedance High (> 9.5V). External SCART source with 4:3 aspect ratio. Normal operation. Pulldown on TV_R/C_OUT is off (power-on default).
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29
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 16. Register 0Dh: Output Enable
DESCRIPTION TVOUT_FS Enable TV_Y/CVBS_OUT Enable TV_B_OUT Enable TV_G_OUT Enable TV_R/C_OUT Enable VCR_R/C_OUT Enable VCR_Y/CVBS_OUT Enable 0 1 0 1 0 1 0 1 0 1 0 1 BIT 7 6 5 4 3 2 1 0 1 0 On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On Off (power-on default) On COMMENTS Off (power-on default)
Table 17. Register 10h: Operating Modes
DESCRIPTION BIT 7 0 0 Operating Mode 1 1 0 1 Full-power mode WITH input video detection and video load detection active. Full-power mode WITHOUT input video detection and video load detection active (power-on default). 6 0 1 5 4 3 2 1 0 Shutdown. Low-power mode with slow switching, CVBS input video detection, and video load detection active only, audio circuitry is off. COMMENTS
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Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Table 18. Register 0Eh: Status
DESCRIPTION BIT 7 6 5 4 3 2 1 0 TV Slow-Switching Input Status 0 1 1 0 VCR Slow-Switching Input Status 0 1 1 Power-On Reset 0 1 0 1 0 1 0 0 1 0 1 0 to 2V, internal source 4.5V to 7V, external source with 16:9 aspect ratio Not used 9.5V to 12.6V, external source with 4:3 aspect ratio 0 to 2V, internal source 4.5V to 7V, external source with 16:9 aspect ratio Not used 9.5V to 12.6V, external source with 4:3 aspect ratio V_DIG is too low for digital logic to operate V_DIG is high enough for digital logic to operate COMMENTS
Table 19. Register 0Fh: Video Activity Status
DESCRIPTION TV CVBS Input Video Detection TV CVBS Output Load VCR CVBS Input Video Detection VCR CVBS Output Load ENC_Y/CVBS_IN Input Video Detection ENC_Y_IN Input Video Detection 0 1 0 1 0 1 0 1 0 1 BIT 7 6 5 4 3 2 1 0 0 1 COMMENTS No video detected Video detected No load connected Load connected No video detected Video detected No load connected Load connected No video detected Video detected No video detected Video detected
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31
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Typical Application Circuit
12V 3.3V 0.1F 3.3V 0.1F 3.3V 0.1F
STB CHIP SDA C
V12
VVID
VAUD TV_OUTR
75 75
TV_OUTL SCL INT
MAX9598
75 TV_SS 75 TV_B_OUT 75 TV_G_OUT 75 TV_R/C_OUT 75 TV SCART
DEV_ADDR
VIDEO ENCODER ENC_Y/CVBS_IN 75
TVOUT_FS 75 TV_Y/CVBS_OUT 0.1F TV_Y/CVBS_IN 75 ENC_R/C_IN 75 75 ENC_G_IN 75 VCR_OUTR 7.68k VCR_INR 2.55k ENC_B_IN VCR_OUTL 75 VCR_INL ENC_Y_IN 75 VCR_SS 0.1F ENC_C_IN 75 0.1F VCR_G_IN 0.1F VCR_R/C_IN 75 75 VCR_R/C_OUT 1F 6.65k ENC_INL R1* 1F 6.65k ENC_INR R1* C1P EP C1N VCR_Y/CVBS_IN CPVSS 1F 1F 75 VCR_Y/CVBS_OUT 0.1F VCRIN_FS 75 75 VCR_B_IN 75 VCR SCART 2.55k 75 7.68k 1F 75 1F GNDVID
STEREO AUDIO DAC
*R1 VALUES DAC = CS4334/5/8/9: R1 = 4.53k 1% DAC = PCM1742: R1 = 5.57k 1%
32
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Low-Power Audio/Video Switch for Dual SCART Connectors
Pin Configuration
TOP VIEW
VCR_R/C_IN TV_G_OUT TV_B_OUT VCR_G_IN ENC_G_IN VCR_B_IN ENC_B_IN VCRIN_FS GNDVID VVID
MAX9598
30 29 28 27 26 25 24 23 22 21 ENC_C_IN 31 ENC_R/C_IN 32 TV_R/C_OUT 33 VCR_R/C_OUT 34 VCR_Y/CVBS_OUT 35 TV_Y/CVBS_OUT 36 VCR_Y/CVBS_IN 37 TV_Y/CVBS_IN 38 ENC_Y_IN 39 ENC_Y/CVBS_IN 40 1 SDA 2 SCL 3 DEV_ADDR 4 INT 5 VAUD 6 C1P 7 C1N 8 CPVSS 9 ENC_INL 10 ENC_INR 20 TVOUT_FS 19 VCR_SS 18 V12 17 TV_SS 16 TV_OUTR
MAX9598
15 VCR_OUTR 14 VCR_OUTL
+
EP*
13 TV_OUTL 12 VCR_INR 11 VCR_INL
THIN QFN (6mm x 6mm)
*EP = EXPOSED PAD
Chip Information
PROCESS: BiCMOS
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33
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Package Information
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. PACKAGE TYPE 40 TQFN-EP PACKAGE CODE T4066+3 DOCUMENT NO. 21-0141
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______________________________________________________________________________________
QFN THIN.EPS
Low-Power Audio/Video Switch for Dual SCART Connectors
Package Information (continued)
For the latest package outline information and land patterns, go to www.maxim-ic.com/packages.
MAX9598
______________________________________________________________________________________
35
Low-Power Audio/Video Switch for Dual SCART Connectors MAX9598
Revision History
REVISION NUMBER 0 1 REVISION DATE 1/08 1/09 Initial release Corrected various errors DESCRIPTION PAGES CHANGED -- 4, 10, 16, 18, 21, 27, 31, 33
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
36 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2009 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.

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